Avery Design Announces CXL™ 2.0 VIP
Avery Design Systems, leader in functional verification solutions today announced availability of CXL 2.0 VIP. Computer Express Link™ (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices
Avery provides a complete System Verilog/UVM verification solution including models, protocol checking, and compliance test suites for PCIe® 5.0 and CXL 2.0/1.1 for CXL host, Type 1-3 devices, switches, and retimers. The CXL 2.0 VIP adds key CXL 2.0 features including
The CXL 2.0 VIP also includes key features including
"We are excited to be working with leading server processor, managed DRAM and storage class memory (SCM) buffers, switch/retimer, and IP companies who are rapidly growing the CXL datacenter ecosystem in 2021 and beyond," said Chris Browy, vice president sales/marketing of Avery. "Our collaboration with IP companies is also critical by creating a best-in-class, robust, pre-validated CXL 2.0 IP controller and PHY solutions and streamlines the design and verification process and fosters the rapid adoption of the CXL standard by the industry." Besides CXL Avery supports the main cache coherent VIPs including CCIX®, AMBA® 5 CHI-E and ACE, and Gen-Z™.
Mobiveil's CXL controller IP (COMPEX™) is a highly configurable, low-latency CXL controller that supports host and device modes for several high-performance applications, such as data center accelerators, memory expanders, artificial intelligence/machine learning and special applications. The COMPEX controller IP is designed for CXL 2.0 specification and supports host and type 1, type 2 and type 3 devices. COMPEX also supports dual mode where it can be configured to operate either as a host or any of the device types.
COMPEX supports up to 16 lanes on a flex bus interface and is compliant with the PIPE 5.2 specification. It provides a simple packet-based interface-to-user logic that supports 128-bit, 256-bit and 512-bit data path widths and provides a low-latency path for easy integration into a customer ASIC. An implementation can choose one of the datapath widths based on the number of lanes and target technology to get low-latency and optimized power consumption from COMPEX controller. For CXL.io, COMPEX uses Mobiveil's PCI (News - Alert)-SIG® compliant GPEX™ controller and adds highly efficient and configurable CXL.mem and CXL.cache layers for a low-latency coherent path.
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Compute Express Link and CXL are trademarks of the CXL Consortium