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EPC2045 100V GaN-on-Silicon Transistor Comparison and Cost Analysis Report 2017 with an Estimation of the Production Cost of the Epitaxy and the Package -
[February 12, 2018]

EPC2045 100V GaN-on-Silicon Transistor Comparison and Cost Analysis Report 2017 with an Estimation of the Production Cost of the Epitaxy and the Package -

The "EPC2045 100V GaN-on-Silicon Transistor: Comparison and Cost Analysis" report has been added to's offering.

The low voltage GaN device market is increasingly important, and Efficient Power Conversion Corporation (EPC) is a major player in low voltage GaN-on-silicon high-electron-mobility transistor (HEMT) devices. 100V GaN HEMTs are a very new technology but they already compete with silicon transistors, especially in the field of megahertz high frequency applications.

The company's EPC2045 device has been investigated, its latest driving 100V for applications such as single-stage 48V converters, USB-C data and power connectors, LiDAR sensors, point-of-load converters and loads in open rack server architectures.

With its new transistor and GaN epitaxy design, the EPC2045 achieves a breakdown voltage of 100V for a current of 16A at 25C, and a very low RdsOn on-resistance of 7m? compared to the previous generation.

The chip-scale packaging of EPC products reduces the final device cost and decreases its inductance, bringing advantages not only with respect to competitors in GaN, but also silicon.

Compared to silicon transistors, GaN process developments have significantly lowered capacitance. This tanslates into lower gate drive losses and lower device switching losses at higher frequencies for the same on-resistance and voltage rating.

Based on a complete teardown analysis, the report also provides an estimation of the production cost of the epitaxy and the package.

The report also compares the new product with previous EPC devices and epitaxy and GaN Systems, Transphorm, Panasonic (News - Alert) and Texas Instruments packaging. This comparison highlights the differences in design and manufacturing processes and their impact on device size and production cost.

Finally, the report shows a comparison between the standard 100V silicon MOSFETs and the EPC GaN-on-silicon HEMT.

Key Topics Covered:

1. Overview/Introduction

2. Executive Summary

Reverse Costing Methodology

3. Company Profile


4. Physical Analysis

Summary of the Physical Analysis

Package analysis

Package opening

Package cross-section


FET die view and dimensions

FET die process

FET die cross-section

FET die process characteristic

Transistor Manufacturing Process

FET Die Front-End Process

FET Die Fabrication Unit

Final Test and Packaging Fabrication Unit

5. Cost Analysis

Summary of the Cost Analysis

Yield Explanations and Hypotheses


FET front-end cost

FET die probe test, thinning and dicing

FET wafer cost

FET die cost Batman: A Freeze Is Coming Christmas Sweater/Jump Complete Device

Packaging Cost

Final Test Cost

Price Analysis

Estimation of Selling Price


Comparison of Epitaxy in GaN

Comparison of Packaging of GaN Transistors

Comparison Between 100V GaN-on-Silicon HEMT and Silicon MOSFETs

For more information about this report visit

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