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Study on Frequency Division Technique of Photoelectric Encoder [Sensors & Transducers (Canada)]
[December 31, 2012]

Study on Frequency Division Technique of Photoelectric Encoder [Sensors & Transducers (Canada)]

(Sensors & Transducers (Canada) Via Acquire Media NewsEdge) Abstract: A scheme to realize frequency division of photoelectric encoder is proposed in this paper. The main idea of the scheme goes like this: the input orthogonal pulse sequence is quadrupled and then divided to form a single-phase frequency sequence. After that, a state machine is designed to convert single-phase signal to orthogonal signal. This scheme can achieve any integral multiple frequency division of orthogonal pulse sequence generated by servo motors or linear scales, etc. Simulation and experiment have been done by using Libro software of Actel Company and its FPGA product APA300. The results show that this scheme is feasible. Copyright © 2012 IFSA.

Keywords: Frequency division, Photoelectric encoder, Electronic gear ratio.

(ProQuest: ... denotes formulae omitted.) 1. Introduction Servo motor is an important execution unit of various numerically-controlled machines. In order to control the exact rotating angle of servo motor, it is a must that the rotating angle of rotor can be detected precisely. Photoelectric encoder is one of the most frequently used angle sensor at present, and it can be divided into incremental, absolute and hybrid types. Due to its easy structure, long service life and easy-to-realize high resolution, etc. incremental type has been widely applied in modern industrial productions. Incremental photoelectric encoder outputs three signals: phase A signal, phase signal and phase signal. Among them, the phase difference of A and is 90°. Phase is the zero position of the encoder and outputs only one pulse for each revolution. In application, it is often needed to divide frequency of the orthogonal pulse of phase A and phase according to certain proportion, i.e. the so-called frequency division. The difficulty of frequency division lies in that whether the set division ratio is integer or fraction, the output of phase A and phase after frequency division should still keep orthogonal or approximately orthogonal.

Frequency division technique of orthogonal signals from incremental photoelectric encoder has attracted lots of researchers to study. For example, a pulsed frequency division technique was proposed in [1] in order to reduce the accumulated error in motion control systems by using Actel FPGA chip EP2C8Q208C8 of Cyclone II. A frequency divider for any coefficient frequency was introduced in [2]. Three kinds of divider consisting of integer frequency divider, decimal frequency divider and fraction frequency divider can be realized by this technique, which can realize different duty cycle and random coefficient. Another division technique was introduced in [3], in which the rotating direction of encoder was considered compared to [2]. All the techniques introduced above can supply satisfied effect. The only uniform shortcoming is mass of consuming of logic gates.

A frequency division technique based on field-programmable gate array (FPGA) is proposed in this paper. This method is simple in logical construction, flexible in configuration and easy to be extended. So it has great practical value. This paper first briefly introduces the concept and functions of electronic gear ratio and frequency division, and then provides the realization idea of frequency division and finally gives the results of simulation and experiment.

This paper is organized as follows: the setting method of electronic gear ratio and frequency division are introduced firstly, and then the realizing principle of frequency division is presented. As an example, the whole part of schematic diagram with set division ratio and corresponding simulation and experiment results are given.

2. Electronic Gear Ratio and Frequency Division Electronic gear ratio and frequency division is an important concept of numerically-controlled machines and CNC machining centers. Most servo drivers abroad are equipped with the function of electronic gear ratio and frequency division. Among them, electronic gear ratio kEG is the ratio of the actually executed pulse and the instruction pulse of the servo driver. Division ratio kDF is the ratio of the pulse which the servo driver receives from the pulse encoder on the motor reel and the actual pulse reflected on upper servo-control system, like CNC. By using electronic gear ratio in concert with frequency division, users can realize integral pulse equivalent to avoid quantization error in the intermediate calculation and transplant code directly to machine tools or processing centers equipped with different number of motor encoder lines or lead screws with different screw pitches without modifying G code.

Electronic gear ratio and frequency division ratio can be calculated according to (1) and (2) [4], ... (1) ... (2) where PG is the number of motor photoelectric encoder lines (unit: Pulse/Revolution); is the screw pitch of lead screw (unit: mm/revolution); Dl is the pulse equivalent (unit: mm/pulse); - is the reduction ratio.

Assumed ... and substitute them into (1) and (2), then get: ...

Electronic gear ratio can be achieved by the frequency conversion of pulse. While for frequency division, as the pulse reflected to CNC by the driver generally adopts orthogonal pulse sequence, the realization of it is more difficult than that of gear ratio. Usually, all kinds of drivers abroad have the function of period diving ratio and after a research and discussion on the realization of frequency division by FPGA, it can be found that the schematic diagram of electronic gear ratio and frequency division function is as shown in Fig. 1 .

3. Realization, Simulation and Experiment Research 3.1. Principle Block Diagram of Frequency Division The realization structure of frequency division function is as shown in Fig. 2. The realization of frequency division needs 3 functional modules: quadruple frequency module (QDPF), frequency dividing module (DF) and orthogonal sequence generation module (OSG). The input of QDPF module is orthogonal pulse sequence and the output pulse of it is direction signal and the pulse after frequency quadrupling. DF module realizes the frequency trisection of input pulse. Inside of DF is a CTUD (Count Up/Down) which can count up and down according to the input direction signal. When the counted numerical value is counted up to the set positive threshold value, a pulse and a positive direction signal will be output; when the counted numerical value is counted down to the set negative threshold, a pulse and a negative direction signal will be output; while when the counted numerical value is between positive and negative threshold value, the output direction signal will not change even if the direction of motor changes or shakes. OSG module triggers the internal state machine to change its status with input pulse edge, determines the status to be jumped to according to input direction signal so as to produce orthogonal signal and direction signal.

3.2. Realization According to Fig. 2, relative functional module is created by using Libro8.1 development platform of ACTEL Company and adopting VHDL hardware language [5, 6]. Schematic diagram is as Fig. 3.

In Fig. 3, PA205 and PA206 are the input pins of phase A and of the original differential signal respectively. Direction signal and pulse signal are output to DF frequency division module after the signal is frequency quadrupled by QDPF, which, after being frequency divided by DF, are output to orthogonal pulse generation module OSG to produce related orthogonal signal A' and B' with phases, and are finally fed back to CNC from PAI 19 and PB 120. Main modules are introduced respectively in the following.

3.3. Simulation and Experiment Quadruple frequency module-QDPF: There are many methods to quadruple the frequency of orthogonal signals and these methods are involved in lots of materials, so this paper will not make detailed introduction here [7, 8].

Frequency dividing module-DF: DF divides the frequency of pulse train input to clkin pin according to the frequency division of initialized setting or the preset frequency division. The internal CTUD (Count Up/Down) counts up (dir_in= 1) or counts down (dir_in=0) the input pulse according to the direction signal input to dirin pin. A pulse and a positive direction signal (dir_out=l) will be output when the count is increased to the positive threshold value while a pulse and a negative direction signal (dir_out=0) will be output when the count is decreased to the negative threshold value. Even if the direction changes repeatedly, namely, no matter the motor reverse or the motor shows shaking within the threshold value, the output direction signal will remain unchanged. This is the key to realize frequency division. If there is something wrong in this step, the motor may send pulse to CNC continuously after its position is fixed. Take one trisection frequency as an example, when the count of counter increases to 3, a positive pulse (positive direction signal + pulse) will be output; when the count of counter decreases to -3, a negative pulse (negative direction signal + pulse) will be output; when the count of counter is between (3/-3), the counter will only count the pulses without output. The simulation result to QDPF is as Fig. 4.

It can be seen from Fig. 4 that, although the direction of motor is always changing, the output direction signals don't change with the change of input direction signals, but change after the set threshold value 3 is reached.

Orthogonal pulse generation module-OSG: OSG realizes the opposite process of quadruple frequency module QDPG and transfers direction + pulse signal to orthogonal signal. Positive rotation makes phase A be 90°ahead of phase B, otherwise the opposite [9]. OSG can be realized through many ways. This paper introduces a simple and reliable method by adopting state machine here.

If the state combination of output signals A' and B' in certain moment is set as one state, orthogonal pulse sequence will have only four states: "00", "01", "10" and "1 1", as shown in Fig. 5. After OSG is triggered by the rising edge of pulse signal, it will jump to the next state according to the present state and the direction signal. When the direction signal is positive, the state can be changed according to counter clockwise direction of the outer ring, producing orthogonal pulse sequence with phase B' being 90°ahead of phase A'. The simulation is as Fig. 6.

In Fig. 6, dir is direction signal, its jumping and changing edge is the position of direction change. The diagram shows that the positive rotating sequence of motor is 10->1 1->01->00 and (opposite direction) ->01->1 1->10. . . which realizes the phase conversion with input signals.

At last, simulate the whole structure of frequency division function and input orthogonal pulse sequence. Input simulated actual motor photoelectric encoder pulse and switch pulse phase repeatedly to verify the output of fixed motor. Simulation is as Fig. 7.

From Fig. 7, it can be seen that when the phase of input signal pula and pulb switch repeatedly, the frequency of output pulal and pulbl is divided according to trisection frequency. New orthogonal sequence should be output after 3 or -3 is met.

Actual experimental waves are as Fig. 8. In Fig. 8, wave pattern 1 and 2 are orthogonal pulses of phase A and phase output by photoelectric encoder. Wave pattern 3 and 4 are respectively orthogonal pulses of phase A' and phase B' after the frequency trisection of orthogonal pulses of phase A and phase B. Longitudinal axis unit: 5V/lattice. Horizontal unit: 1 .2 seconds/lattice. Observe diagram 7 and 8, and the results are the same. The realized frequency division with this method has been successfully used in high-precision servo drivers. No deviation is found in the repeated verification of actual application.

4. Conclusion A scheme to realize frequency division of photoelectric encoder is proposed in this paper. By this technique, the function block is divided to 3 modules: quadruple frequency module QDPF, frequency dividing module DF, and orthogonal pulse generation OSG module. Orthogonal signal from incremental photoelectric encoder is quadrupled by QDPF firstly, to convert orthogonal pulse to a single pulse sequence. After that, the single pulse sequence is divided using an integer, fraction or decimal divider. At last, the divided single pulse sequence is converted to orthogonal pulse by OSG. As an example, a 1/3 frequency division is realized by using Actel FPGA chip, and the simulation/experiment result are given According to the simulation/experiment result it can be seen that, 1. the proposed scheme can achieve any integer frequency division. 2. This scheme is simple in logical construction, flexible in configuration and easy to be extended. Fig. 9 shows photography of experiment platform. In actual system, MCU can also be used to configure frequency division online through the BUS. If you want to realize the frequency division of fraction proportion, all you shall do is to make a little improvement on the basis of this scheme.

Acknowledgements The author wish to acknowledge the support by the Science Foundation of Henan University of Technology.

References [1]. Bai Yingjie, Du Jianming and Luo Yixing, Study on Pulse Division Technique Base on FPGA, Microcomputer Application, Vol. 31, Issue 3, 2010, pp. 67-71.

[2]. Zhou Dianfeng, Kang Sucheng and Wang Junhua, Design of Universal Frequency Divider Based on FPGA, Informatization Research, Vol. 36, Issue 2, 2010, pp. 59-61.

[3]. Quan Jie, Yin Quan, Realization of Fraction Divider for Photoelectric Decoder, Servo Control, Issue 9, 2008, pp. 58-60.

[4]. Yaskawa Electric, S-II Series SGMXH/SGDM User 's Manual, 2003.

[5]. Xin Chunyan, VHDL Hardware Description Language, National Defense Industrial Publishing House, 2002.

[6]. Qi Jingli, Song Yifang and Chen Jiansi, Application of VHDL Language in FPGA, Microcomputer Information, Vol. 22, Issue 12, 2006, pp. 149-151.

[7]. Dong Lili, Xiong Jingwu and Wan Qiuhua, Development of Photoelectric Rotary Encoders, Optics Precision Engineering, Vol. 8, Issue 2, 2000, pp. 198-204.

[8]. Tang Yaping, The Design of Equal Precision Digital Cymometer Based on FPGA and DSP, Microcomputer Information, Vol. 23, Issue 1, 2007, pp. 249-251.

[9]. Zhang Qiong, Yang Qing and Bi Guihong. Design of Intelligent High-accuracy Pulse Width Digital Filtering Circuit, Automation Instrumentation, Vol. 27, Issue 6, 2006, pp. 53-58.

1 Shi-Xiong Zhang, l Bing-Sheng Yan, 1 Yan-Fang Guan 1 School of Mechanical & Electrical Engineering, Henan University of Technology, No. 195, Zhongyuan Rd., Zhengzhou, 450007, China Tel.:+86-371-67758631 E-mail:, en. yfg8 Received: 11 September 2012 /Accepted: 11 October 2012 /Published: 20 November 2012 (c) 2012 International Frequency Sensor Association

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