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Jasper Design Automation's Kathryn Kranen Moderates DAC Pavilion Panel on Today's Consumer at the 45th Annual Design Automation Conference
[June 09, 2008]

Jasper Design Automation's Kathryn Kranen Moderates DAC Pavilion Panel on Today's Consumer at the 45th Annual Design Automation Conference


MOUNTAIN VIEW, Calif. --(Business Wire)-- Jasper Design Automation:
WHO:
  Jasper Design Automation, the leader in successful deployment of
  production proven formal verification solutions, today announced
  that president and CEO, Kathryn Kranen, will moderate a unique
  panel on today's consumers.
WHAT:
  The DAC pavilion panel is entitled, "Today's Consumers: High
  Schoolers Spec Your Next Product" and will feature speakers Justin
  Towers, Jon Michael Guay and Brett Davis, all students at Servite
  High School in Anaheim, California.
  "We all want to design the new hot consumer device like the iPod
  or the Wii. Today's consumers are college students and high
  schoolers, and they think very differently from you. This panel
  features tech savvy Java programming students. Hear what these
  high schoolers find cool in current devices and what they want in
  the future."
WHEN:
  June 9th, 3:00pm - 3:34pm
WHERE:
  Pavilion Stage, Booth # 364, Anaheim Convention Center, Anaheim,
  California
  For details visit:
  






">http://www.dac.com/events/eventdetails.aspx?id=77-104.


About Jasper Design Automation


Jasper Design Automation's production proven formal verification solutions are used by logic designers, verification engineers and silicon bring-up teams to design, explore and debug RTL, to ensure correctness of block-level functionality and for rapid post-silicon validation and debug. JasperGold(R) Verification System delivers complete "deep formal" systematic verification, ensuring correctness of critical design features without any testbench development. JasperGold Express, a "light formal" solution, complements simulation by accelerating bug-hunting and coverage attainment. For expert help with large scale formal verification deployment, RTL exploration or post-silicon debug, please visit http://www.jasper-da.com.

Jasper Design Automation, the Jasper Design Automation logo, JasperGold, Formal Testplanner, GamePlan, Proof Accelerators, Lossless Abstractions, Formal Scoreboard, and Design Tunneling are trademarks or registered trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.

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