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Avery Design Systems Announces NVMe 1.3 and NVMe-MI Verification IP Updates
[August 07, 2017]

Avery Design Systems Announces NVMe 1.3 and NVMe-MI Verification IP Updates

Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of updates to its NVMe VIP supporting NVMe 1.3 and support for new NVMe-Management Interface (NVMe-MI) over PCIe 4.0 or SMBus 3.0.

The NVMe VIP now supports the NVMe 1.3 standard including enhancements to models, protocol checking, and compliance testsuites.

NVMe 1.3 mandatory features and revisions

  • Identify Namespace return list of Namespace Identifiers
  • Get Log Page command change for Retain Asynchronous Event functionality
  • Globally Unique Updates
  • SGL Dword Simplification
  • Firmware Update Granularity
  • Namespace Optimal IO Boundary
  • Non-Operational Power State Permissive Mode
  • Data Transfer Direction for opcodes shall be valid
  • Reservations Changes
  • Operation Denied status code
  • Deallocated Value for Logical Block Data

NVMe 1.3 optional new features

  • Device Self-Test
  • Sanitize
  • Directives
  • Boot Partitions
  • Telemetry
  • Virtualization Enhancements
  • NVMe-MI Management Enhancements
  • Host Controlled Thermal Management
  • Timestamp
  • Emulated Controller Performance Enhancement

The NVMe host driver now supports the NVMe Management Interface (NVMe-MI) to communicate out-of-band with an NVMe NVM Subsystem Management Endpoint via PCI (News - Alert) Express or SMBus/I2C over a simplified MCTP protocol. NVMe-MI supports a native PCIe in-line flow or SMBus adapter for out-of-bound communication via a SMBus 3.0 host model.

  • Discover devices that are present and learn capabilities of each device
  • Store data about the host environment enabling a Management Controller to query the data later
  • Health and temperature monitoring
  • Multiple Command Slots to prevent a long latency command from blocking monitoring operations
  • Processor (News - Alert) and operating system agnostic
  • A standard format for VPD and defined mechanisms to read/write VPD contents
  • Preserves data at rest security

"Avery continues to demonstrate leadership in NVMe and PCIe VIP with support for the latest NVMe features," said Chris Browy, vice president of sales/marketing at Avery. "Our customers can develop new products more confidently and quickly knowing a comprehensive SystemVerilog/UVM NVMe verification environment is available for the latest in NVMe developments targeting enterprise, client, and cloud."

See Avery Design Systems at Flash Memory Summit (Booth #718), August 8-10, at the┬áSanta Clara Convention Center, Santa Clara, CA (News - Alert).

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, CCIX, USB, AMBA, UFS, Unipro, CSI-2/DSI-2, Soundwire, Sensewire, DDR/LPDDR, HBM, HMC, ONFI/Toggle, NVM Express, SAS (News - Alert), SATA, eMMC, SD/SDIO, CAN FD, LIN, FlexRay, HDMI, and DisplayPort standards. The company is a member of the Mentor Graphics Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at

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