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The availability of Sprint (News - Alert)'s C3PO or Clean CUPS Core for Packet Optimization – CUPS: Control & User Plane Separation – comes after four years of research into Network Functions Virtualization (NFV) and software-defined networking (SDN). The announcement by Sprint revealed the new open source platform is going to, according to the company, provide a clean, streamlined and high-performance data plane for the packet core to significantly improve the performance of the network.

The C3PO development is a collaboration between Sprint and Intel (News - Alert) Labs that was created as a joint research effort to develop optimal Data Plane Development Kit (DPDK)-based data plane nodes and disaggregated evolved packet core architectures with a platform to eventually advance 5G core infrastructure research. With 5G deployments fast approaching, network operators, telecoms and enterprises are all looking for network optimization solutions.

"C3PO revolutionizes the network core and it’s part of our expanded toolbox of solutions to meet the coming wave of data in the years ahead. C3PO is an important part of our NFV and SDN initiative, enabling Sprint to adapt more quickly to market demands and scale new services more efficiently and cost-effectively," said Günther Ottendorfer, Chief Operating Officer – Technology, Sprint.

According to Dr. Ron Marquardt, Vice President of Technology at Sprint, with the combined technologies of Sprint and Intel, they have developed a single solution that provides seven functions previously located within separate physical elements, while streamlining traditional mobility architectures and software designs to be more efficient and scalable.

With the C3PO architecture, network bottlenecks will be reduced in mobile core packet performance by separating and independently scaling the data plane and control plane. It does this by collapsing multiple evolved packet core and SGi LAN elements, including serving gateway, packet gateway, deep packet inspection, child protection, carrier grade NAT or any combination of these functions into one data plane instance.

Using standard high-volume server hardware, in this case the Dell EMC (News - Alert) DSS 9000 rack scale infrastructure with compute sleds running dual socket 14 core Intel Xeon processors E5-2680 v4, Sprint achieved 1.63 Mpps (million packets per second) throughput in a lab test.

As part of the collaborative process, Sprint developed the SDN controller enhancements and Intel Labs technologists built the next generation core control plane and data plane virtualized EPC applications. They are both available as an open source project, with Intel placing the EPC application code in the CORD project in ON (News - Alert).Lab, while Sprint's SDN plug-ins are available via OpenDaylight.