This article originally appeared in the Dec. 2012 issue of INTERNET TELEPHONY

Intel’s (News - Alert) new Xeon E3 and E5 series microprocessors, code named Sandy Bridge, are changing how deep packet inspection applications run and perform on server platforms. General-purpose microprocessors have traditionally served within the control plane of communications and networking equipment, leaving ASICs, FPGAs and various accelerator cards to handle packet processing in the data plane. Intel’s faster and more efficient Xeon E3/E5 processors are better equipped to handle deep packet inspection security algorithms and will replace many of the network processors commonly used in today’s enterprise- and carrier-class servers.

Changes to Intel’s Xeon E3 and E5 series microprocessors include new instructions to accelerate common encryption tasks and floating point calculations, as well as increased core counts and cache per CPU. Intel’s processor enhancements are also transforming how pre-integrated server application software interoperates with on-board memory, disk drives, RAID controllers, and the operating system.

The E3 and E5 series of Xeon CPUs are based on a new microprocessor architecture that is manufactured on Intel’s 32 nm geometry process. The technology is designed to enhance a range of applications that run on notebooks, desktop computers, and enterprise-class servers. The new architecture has been trial-demonstrated to provide up to 17 percent more CPU performance (clock-for-clock) compared to Lynnfield 45 nm quad-core Xeon X34xx processors.

Additionally, the Xeon E3 and E5 series is optimized to deliver up to 60 percent more performance and 30 percent greater energy efficiency compared to its predecessor. With more available cores, each core running faster, built-in PCI (News - Alert) Express 3.0 capability, more memory channels and faster QuickPack Interconnects, this new micro-architecture has the potential to create entirely new application categories.

So what's the final score?  

The E3 and E5 series processors’ ability to increase CPU processing, memory, and I/O performance, while reducing bottlenecks for applications that demand real-time data rates, make them better equipped to handle deep packet inspection algorithms that support network port expansion.

Jeff Hudgins (News - Alert) is vice president of product management at NEI Inc. (www.nei.com).