Top Three Considerations When Adopting Intel's New Micro Architecture

Tech Score

Top Three Considerations When Adopting Intel's New Micro Architecture

By Jeff Hudgins, VP of Engineering, NEI, Inc.  |  April 25, 2012

This article originally appeared in the April 2012 issue of INTERNET TELEPHONY magazine.

Intel's (News - Alert) newly announced Xeon E3, E5 and E7 series of microprocessors, based on its Sandy Bridge micro architecture, is changing how software applications run and perform on server platforms. These CPUs require significant source code changes. Is your company’s application development team ready and able to unleash the power of these new devices? 

Here are three important considerations to help guide some of the transition thinking.

First, unlike the previous Nehalem to Westmere refresh, this architecture requires completely new hardware platforms. Developers must allocate sufficient budget to obtain hardware platforms for testing. But that's only the start. Allocating test engineering resources to conduct performance and interoperability tests along with marketing resources to update datasheets, websites, and product manuals can easily blow the budget. And leaving obsolete inventory behind is a direct hit to the bottom line, so proper timing and execution are critical.

Second, software applications that have traditionally been plagued by memory bottlenecks can now see greater benchmark performance on the new micro architecture. The memory read bandwidth has doubled as compared to the prior generation of processors with the addition of a memory read port. Early adopters can gain a significant competitive advantage, so look for ways to code optimize around the increased memory performance.

Lastly, general-purpose microprocessors have traditionally served within the control plane of communications and networking equipment, leaving ASICs, field-programmable gate arrays, and various accelerator cards to handle packet processing in the data plane. But that is all beginning to change as Intel’s faster and more efficient processors aim to replace many of the packet processing chipsets commonly used in today’s enterprise- and carrier-class servers.

So what's the final score? Sandy Bridge is designed to enhance a range of applications that run mobile devices, laptops, and enterprise-class servers. Developers have a chance to realize increased performance and cost savings, but it will take a well thought out transition plan to capture the power of these new devices.






Edited by Jennifer Russell
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