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OneSpin's Formal Verification Expertise Showcased in May at ChipEx, DVClub, SEE/MAPLDMUNICH and SAN JOSE, Calif. , April 26, 2018 (GLOBE NEWSWIRE) -- OneSpin® Solutions, provider of innovative formal verification solutions for highly reliable, digital integrated circuits (ICs), will showcase its expertise in May at ChipEx2018, DVClub Europe and SEE/MAPLD. ChipEx will be held Tuesday, May 1, at the Tel Aviv Convention Center, Tel Aviv, Israel, from 8 a.m. until 4:30 p.m. OneSpin will exhibit and demonstrate its comprehensive formal verification solutions, including Safety Critical Verification, Quantify™ Fault Observation Coverage, SystemC/C++ Design Verification, and Field Programmable Gate Array (FPGA) Implementation Verification. Nicolae Tusinschi, OneSpin’s product specialist design verification, will present “Meeting the Challenge: Formal Verification of an FPU” at DVClub Europe Tuesday, May 15. Attendees can participate online or in perso at locations in Bristol and Cambridge, U.K., and Grenoble, France. OneSpin will exhibit at SEE/MAPLD (Single Event Effects Symposium/Military and Aerospace Programmable Logic Devices Workshop) at the Marriott La Jolla in San Diego, Calif. The exhibition will run during meal and coffee breaks between technical sessions Tuesday, May 22, from 9:30 a.m. to 8 p.m. and Wednesday, May 23, from 9:30 a.m. until 1 p.m. David Landoll, OneSpin's solutions architect, will present “Formal Sequential Equivalence Checking for Highly Optimized Safety-Critical FPGAs” Wednesday, May 23, at 9:40 a.m. He also will present “Mitigating Single Event Effects to Meet Functional Safety Standards” during the SEE/MAPLD poster session the same day from 5 p.m. to 8 p.m. About OneSpin Solutions Engage with OneSpin at: OneSpin, OneSpin Solutions and the OneSpin logo are trademarks of OneSpin Solutions GmbH. All other trademarks are the property of their respective owners. For more information, contact: |