TMCnet News
Microsemi Collaborates with MathWorks to Deliver First Integrated FPGA-in-the-Loop Workflow for PolarFire and SmartFusion2 FPGA Development BoardsALISO VIEJO, Calif., April 19, 2018 /PRNewswire/ -- Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced its collaboration with MathWorks®, a leading developer of mathematical computing software for engineers and scientists, to launch hardware support for field programmable gate array (FPGA)-in-the-loop (FIL) verification workflow with Microsemi FPGA development boards. The new integrated FIL workflow with HDL Coder™ and HDL Verifier™ from MathWorks enables customers to automatically generate test benches for hardware description language (HDL) verification, including VHSIC Hardware Description Language (VHDL) and Verilog, providing rapid prototyping and verification of designs. The collaboration with MathWorks enables customers to integrate MATLAB®, a programming environment for algorithm development, data analysis, visualization and numeric computation, and Simulink®, a graphical environment for simulation and Model-Based Design, with Microsemi's SmartFusion™2 system-on-chip (SoC) FPGA and PolarFire® FPGA development boards, which allows the stimulation of designs through FIL verification workflow using Microsemi's development boards. FIL verification workflow enables customers to analyze the results back in MATLAB and Simulink. "With the ever-increasing complexity in algorithm designs, it has become imperative for designers to quickly design and validate their algorithms on real hardware," said Shakeel Peera, vice president FPGA marketing for Microsemi. "This integrated FPGA-in-the-loop workflow of Microsemi FPGA boards with MathWorks HDL Verifier will allow system engineers and algorithm developers to quickly prototype and implement their MATLAB and Simulink designs on Microsemi FPGA development boards through our Libero SoC Design Suite." Microsemi's collaboration with MathWorks enables a unified workflow to verify designs comprehensively. It integrates Microsemi's Libero SoC Design Suite—a comprehensive, easy to learn, easy to adopt development toolset for designing with Microsemi's FPGAs and SoC FPGAs—with MATLAB and Simulink for design verification, and provides FIL verification with Microsemi FPGA boards. This allows customers to catch bugs early in the design cycle, helping reduce time to market and enabling early verification. "MATLAB and Simulink are widely used by engineers to develop algorithms targeting FPGAs," said Paul Barnard, director of marketing for the Simulink product family at MathWorks. "Now that HDL Verifier supports FIL for Microsemi development kits, engineers can connect designs implemented on these FPGA boards directly to MATLAB and Simulink test benches, streamlining a crucial validation step in developing safety-critical avionics, space and other applications." Delivering the industry's first FIL feature for Microsemi boards with MATLAB and Simulink, the collaboration provides HDL Verifier Support Package for Microsemi FPGA, a hardware support package for SmartFusion2 SoC FPGA and PolarFire FPGA development boards, and an integrated workflow from algorithms to implementation. Leveraging HDL Verifer, enabled by Microsemi's Accelerate Ecosystem, makes Microsemi's FPGAs ideal for a wide variety of applications within the aerospace and defense, security, industrial and medical markets, including motor control and imaging, digital signal processing, communication systems, machine vision and imaging systems, control systems, military communications, and payload and radio processing. The usage of FPGA verification significantly reduces timelines and development costs and has experienced considerable adoption in defense, automotive and industrial markets, leading to a booming $68 million for FPGA verification since September 2017 (as of March 2018), growing at a compound annual growth rate (CAGR) of nearly 8 percent through 2025 according to IndustryARC. The market research firm also notes FPGA verification has an untapped potential market (total addressable market, or TAM) of $425 million with a tapped service addressable market (SAM) of $141 million. About Microsemi's Accelerate Ecosystem Product Availability About Microsemi's FPGAs About Microsemi Microsemi and the Microsemi logo are registered trademarks or service marks of Microsemi Corporation and/or its affiliates. Third-party trademarks and service marks mentioned herein are the property of their respective owners. "Safe Harbor" Statement under the Private Securities Litigation Reform Act of 1995: Any statements set forth in this news release that are not entirely historical and factual in nature, including statements related to its collaboration with MathWorks, a leading developer of mathematical computing software for engineers and scientists, to launch hardware support for field programmable gate array (FPGA)-in-the-loop (FIL) workflow with Microsemi development boards, and its potential effects on future business, are forward-looking statements. These forward-looking statements are based on our current expectations and are inherently subject to risks and uncertainties that could cause actual results to differ materially from those expressed in the forward-looking statements. The potential risks and uncertainties include, but are not limited to, such factors as rapidly changing technology and product obsolescence, potential cost increases, variations in customer order preferences, weakness or competitive pricing environment of the marketplace, uncertain demand for and acceptance of the company's products, adverse circumstances in any of our end markets, results of in-process or planned development or marketing and promotional campaigns, difficulties foreseeing future demand, potential non-realization of expected orders or non-realization of backlog, product returns, product liability, and other potential unexpected business and economic conditions or adverse changes in current or expected industry conditions, difficulties and costs of protecting patents and other proprietary rights, inventory obsolescence and difficulties regarding customer qualification of products. In addition to these factors and any other factors mentioned elsewhere in this news release, the reader should refer as well to the factors, uncertainties or risks identified in the company's most recent Form 10-K and all subsequent Form 10-Q reports filed by Microsemi with the SEC. Additional risk factors may be identified from time to time in Microsemi's future filings. The forward-looking statements included in this release speak only as of the date hereof, and Microsemi does not undertake any obligation to update these forward-looking statements to reflect subsequent events or circumstances.
View original content with multimedia:http://www.prnewswire.com/news-releases/microsemi-collaborates-with-mathworks-to-deliver-first-integrated-fpga-in-the-loop-workflow-for-polarfire-and-smartfusion2-fpga-development-boards-300632618.html SOURCE Microsemi Corporation |