High-density Packaging (MCM, MCP, SIP, 3D-TSV): Market Analysis and Technology Trends 2018

DUBLIN, Jan. 9, 2018 /PRNewswire/ --

The "High-Density Packaging (MCM, MCP, SIP, 3D-TSV): Market Analysis and Technology Trends" report has been added to Research and Markets' offering.

This report discusses the packaging trends for higher performance and density driving advanced packaging technology solutions for mobile and IoT applications. One of the key enabling technologies to achieve these goals is thin 3D-packaging with integration. Developments have lately been made with various embedding technologies, such as eWLB/Fan out WLP and embedded devices.

The explosion of applications in the consumer and mobile space, internet of things (IoT) and the slowdown of Moore's law have been driving many new trends and innovations in packaging. The semiconductor industry now has to focus on system scaling and integration to meet the ever-increasing electronic system demands for performance and functionality, and for reduction of system form factor, system power consumption and system cost.

This paradigm shift from chip-scaling to system-scaling will re-invent microelectronics, continue driving system bandwidth and performance, and help sustain Moore's Law. The challenge for semiconductor industry is to develop a disruptive packaging technology platform capable of achieving these goals.

Higher integration levels and lower profiles are also achieved with wafer-level processes, at which most R&D is concentrated in the commercialization of 2.5D ICs (with silicon interposer) & 3D ICs, as well as coreless substrate. Furthermore, there is tremendous pressure to decrease overall package height even with the additional dies stacking through innovation in wafer thinning, TSV, and ultrathin interconnects.

Key Topics Covered:

Chapter 1 Introduction

Chapter 2 Executive Summary

2.1 Summary of Technology Issues
2.2 Summary of Market Forecasts

Chapter 3 Technology Issues and Trends

3.1 Overview of HDP Technology
3.1.1 Need for Multiple IC Integration
3.1.2 Challengs of Multiple IC Integration

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