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RISC-V Ecosystem to Present at 15th International System-on-Chip (SoC) Conference, Exhibit & Workshops
RISC-V Foundation:
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WHERE:
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The 15th International System-on-Chip (SoC) Conference, Exhibit &
Workshops, University of California, Irvine (UCI) , Irvine, Calif.,
92697, Calit2 Building 2
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WHEN:
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Wednesday, Oct. 18 to Thursday, Oct. 19, 2017
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WHAT:
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The RISC-V Foundation will feature six member organizations at
this year's International SoC Conference. Ted Speers, VP and Head
of Product Architecture and Planning for Microsemi (News - Alert) SoC Group, a
founding RISC-V member, is a keynote speaker addressing the
challenges and possibilities of the open, free RISC-V ISA.
Additionally, Foundation members including Codasip, Dover
Microsystems, Imperas, SiFive and UltraSoC will present at this
year's show. RISC-V speaking sessions include:
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Keynote: "RISC-V Challenges and Possibilities
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When: Wednesday, Oct. 18, 2017 at 1 - 1:50 p.m. PT
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Who: Ted Speers at Microsemi
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Introducing the New RISC-V U54 Coreplex
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When: Wednesday, Oct. 18, 2017 at 1:50 - 2:20 p.m. PT
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Who: Jack Kang at SiFive
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RISC-V Models and Simulation Enable Early Software Bring Up
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When: Wednesday, Oct. 18, 2017 at 2:20 - 2:50 p.m. PT
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Who: Larry Lapides at Imperas Software Ltd.
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System-wide Visibility and Analytics
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When: Wednesday, Oct. 18, 2017 at 2:50 - 3:20 p.m. PT
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Who: Gajinder Panesar at UltraSoC
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The Dover PIPE: Processor (News - Alert) Interlocks for Policy Enforcement
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When: Wednesday, Oct. 18, 2017 at 3:30 - 4 p.m. PT
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Who: Steven Milburn at Dover Microsystems
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A High-Level Design Methodology for RISC-V Processor Development
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When: Wednesday, Oct. 18, 2017 at 4 - 4:30 p.m. PT
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Who: Dan Ganousis at Codasip
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RISC-V and prpl: Why RISC-V will Become the Most Secure Processor
Architecture
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When: Thursday, Oct. 19, 2017 at 4 - 4:30 p.m. PT
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Who: Art Swift (News - Alert) at prpl Foundation
To schedule a meeting with RISC-V or a member organization please email: [email protected].
To learn more about the RISC-V Foundation, its open, free architecture
and membership information, please visit: https://riscv.org.
About RISC-V Foundation
RISC-V (pronounced "risk-five") is an open, free ISA enabling a new era
of processor innovation through open standard collaboration. Founded in
2015, the RISC-V Foundation comprises more than 70 member organizations
building the first open, collaborative community of software and
hardware innovators powering innovation at the edge forward. Born in
academia and research, RISC-V ISA delivers a new level of free,
extensible software and hardware freedom on architecture, paving the way
for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its
members, directs the future development and drives the adoption of the
RISC-V ISA. Members of the RISC-V Foundation have access to and
participate in the development of the RISC-V ISA specifications and
related HW / SW ecosystem.
View source version on businesswire.com: http://www.businesswire.com/news/home/20171018005002/en/
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