TMCnet News
Docea Power Reveals Aceplorer 4.0 and Thermal Profiler 4.0 to Speed Up Power and Thermal Management Policies Development and Validation at DAC52Docea Power, the provider of virtual prototyping solutions for power and thermal, will reveal at the 52nd Design Automation Conference (DAC) the latest releases of its Aceplorer and Thermal Profiler software tools. Docea Power will demonstrate new advances in power and thermal management modeling and simulation with Aceplorer 4.0 and Thermal Profiler 4.0 new solvers to speed up thermal verification.
Aceplorer 4.0 features a new programming interface, the PTM-API
(Power and Thermal Management Application Programming Interface) for
modeling complex power and thermal management algorithms (e.g. Android (News - Alert)
Governors, CPUFreq, CPUIdle). This feature enables to simulate the
performance of a chipset given a specific power management policy.
A major issue for chipset vendors and OEMs is to predict the real performance of their devices on a thermally constrained environment. In many devices (e.g. mobile chipsets, automotive ICs), high performance modes can only be sustaine for a limited time. The real devices' performance is the result of a mix between high speed and low power modes. This mechanism is called thermal mitigation (or throttling) and must be characterized and optimized. Docea Power provides unique solutions for thermal throttling modeling and simulation thanks to compact thermal models generated by the Thermal Profiler, Aceplorer coupled power and thermal simulator and the new PTM-API to model power and thermal management policies. The Thermal Profiler 4.0 release is augmented with new steady state and step response solvers that facilitate the validation of thermal models imported from CFD tools before generating a compact thermal model for fast dynamic simulations. In addition, Docea Power solutions will be presented in the following events: DESIGNER AND IP TRACK Presentation:
Session 25. INNOVATIVE FRONT-END DESIGN AND VALIDATION AT SYSTEM LEVEL. DESIGNER AND IP TRACK POSTER: Interactive presentations:
31.36 System Level Thermal Analysis Platform for Mobile SoC
31.69 Architectural Trade-Off Analysis
PRODUCT DEMONSTRATIONS
View source version on businesswire.com: http://www.businesswire.com/news/home/20150529005768/en/ |