[May 21, 2013] Blue Pearl Software Opens Office in Texas Tweet May 21, 2013 (Close-Up Media via COMTEX) -- Blue Pearl Software, the provider of EDA software that accelerates FPGA design verification, announced it has opened an office in Texas. According to a release Richard Gary, an EDA industry veteran, will head the newly opened office. Richard Gary has sales and sales management experience with success at startups and major companies. Over the years, he has provided excellent support for his local customers while he worked for companies like Zeland, Mentor Graphics, Magma, Cadence Design Systems, and Cooper & Chyan Technology. "By adding a skilled professional like Richard to the central region, we continue to provide local support for our growing customer base," said Roger Bitter, Vice President Worldwide Sales, Blue Pearl Software. "Richard's hands-on approach to sales and his understanding of the market will be invaluable to both customers and to Blue Pearl Software." "We are committed to providing innovative solution to solve the FPGA verification challenges that designers encounter every day," noted Richard Gary. "The Blue Pearl Software Suite is not only easy to use, but its integration in major FPGA design flows ensures minimal ramp-up time." The Company said the Blue Pearl Software Suite works with the Xilinx Vivado Design Suite running on Windows platforms. It includes linting, CDC analysis and automatic SDC generation. Its generated SDCs drive the efficiency of the synthesis and place and route phases of FPGA design implementation, and reduce iterations and overall design time. Its Visual Verification Environment makes it easy to use. The company's collaboration with Synopsys offers an optimized flow that works with Synopsys' Synplify Pro FPGA synthesis software. Verilog, VHDL and SystemVerilog designers can automatically generate an exhaustive set of constraints that address false and multi-cycle paths that are compatible with Synopsys' synthesis flow. Blue Pearl Software, Inc. provides EDA software that accelerates FPGA design verification. The company's Blue Pearl Software Suite checks RTL designs for functional errors and automatically generates Synopsys Design Constraints (SDC) to improve quality of results (QoR) and reduce FPGA design risks. More information: www.bluepearlsoftware.com ((Comments on this story may be sent to [email protected])) [ Back To TMCnet.com's Homepage ]