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U.S. Patents Awarded to Inventors in Oregon (Feb. 27)
[February 27, 2013]

U.S. Patents Awarded to Inventors in Oregon (Feb. 27)

(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., Feb. 27 -- The following federal patents were awarded to inventors in Oregon.

*** Palo Alto Research Center Assigned Patent ALEXANDRIA, Va., Feb. 27 -- Palo Alto Research Center, Palo Alto, Calif., has been assigned a patent (8,386,486) developed by four co-inventors for a "method for facilitating social networking based on fashion-related information." The co-inventors are Wei Zhang, Corvallis, Ore., Takashi Matsumoto, Tokyo, Maurice K. Chu, San Mateo, Calif., and James M. A. Begole, San Jose, Calif.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "One embodiment of the present invention provides a system for facilitating social networking based on fashion-related information. During operation, the system receives fashion-related information from a user. Next, the system extracts the user's fashion preferences from the received information and compares the user's fashion preference with other users' fashion preferences. Finally, the system groups users based on similarity of their fashion preferences." The patent application was filed on July 2, 2008 (12/166,581). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,86,486.PN.&OS=PN/83,86,486&RS=PN/83,86,486 Written by Amal Ahmed; edited by Jaya Anand.

*** Yahoo! Assigned Patent for System and Method for Context Enhanced Messaging ALEXANDRIA, Va., Feb. 27 -- Yahoo!, Sunnyvale, Calif., has been assigned a patent (8,386,506) developed by seven co-inventors for a "system and method for context enhanced messaging." The co-inventors are Ronald Martinez, San Francisco, Marc Eliot Davis, San Francisco, Michael Spiegelman, Los Angeles, Christopher T. Paretti, San Francisco, Nicola Stefano Ghezzi, Santa Monica, Calif., Christopher William Higgins, Portland, Ore., and Chris Kalaboukis, Los Gatos, Calif.


The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system and method for media enhanced messaging. A message from a message sender to be delivered to at least one message recipient is received over a network. The message comprises at least one delivery criteria and at least one content criteria. When it is determined, via the network that the delivery criteria of the message has been satisfied, a query is formulated based on the content criteria so as to search, via the network, for user profile data, social network data, spatial data, temporal data and topical data that is available via the network and relates to the content criteria and to media files so as to identify at least one media file that is relevant to the content criteria. The media files are inserted into the message and the message is transmitted over the network to the recipient." The patent application was filed on Aug. 21, 2008 (12/195,969). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,86,506.PN.&OS=PN/83,86,506&RS=PN/83,86,506 Written by Amal Ahmed; edited by Jaya Anand.

*** International Business Machines Assigned Patent for Standby Index in Physical Data Replication ALEXANDRIA, Va., Feb. 27 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,386,462) developed by four co-inventors for a "standby index in physical data replication." The co-inventors are Prasadarao Akulavenkatavara, Portland, Ore., Aaron I. Henner, Beaverton, Ore., Gary N. Jin, Portland, Ore., and Steven R. Pearson, Portland, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Generating a standby index on a standby database server in a physical log-shipping data replication environment. Embodiments of the invention include providing a primary database server and a standby database server, replicating a primary database and a primary database index from the primary database server to the standby database server, generating a standby index on the standby database server, and cataloging the standby index on the standby database server." The patent application was filed on June 28, 2010 (12/825,264). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,86,462.PN.&OS=PN/83,86,462&RS=PN/83,86,462 Written by Amal Ahmed; edited by Jaya Anand.

*** Intel Assigned Patent for Method for Trimming Data on Non-volatile Flash Media ALEXANDRIA, Va., Feb. 27 -- Intel, Santa Clara, Calif., has been assigned a patent (8,386,537) developed by James A. Boyd, Hillsboro, Ore., and Knut S. Grimsrud, Forest Grove, Ore., for a "method for trimming data on non-volatile flash media." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for trimming data on non-volatile flash media is generally presented. In this regard, in one embodiment, a method is introduced comprising allocating a temporary file that occupies free space on a flash memory, determining specific blocks of the flash memory that the temporary file occupies, generating TRIM commands for the specific blocks, and deleting the temporary file. Other embodiments are described and claimed." The patent application was filed on Dec. 15, 2009 (12/638,496). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,86,537.PN.&OS=PN/83,86,537&RS=PN/83,86,537 Written by Amal Ahmed; edited by Jaya Anand.

*** Yahoo! Assigned Patent for System and Method for Modeling Relationships between Entities ALEXANDRIA, Va., Feb. 27 -- Yahoo!, Sunnyvale, Calif., has been assigned a patent (8,386,499) developed by four co-inventors for a "system and method for modeling relationships between entities." The co-inventors are Ronald Martinez, San Francisco, Marc Eliot Davis, San Francisco, Christopher William Higgins, Portland, Ore., and Joseph James O'Sullivan, Oakland, Calif.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "The disclosure describes systems and methods for modeling relationships between entities on a network using data collected from a plurality of communication channels including social data, spatial data, temporal data and logical data within a W4 Network. The W4 Network personalizes and automates sorting, filtering and processing of W4COMN communications delivered or requested to be delivered using personalized value-based ranking and encoding of data, which is modeled from the point-of-view (POV) of any specific user, topic or node in the W4 Distributed graph. POV modeling supplies comparative value services to users which entails individuated data models to be aggregated and used in customization and personalization forecasting for each user and their associated data management needs." The patent application was filed on Aug. 20, 2012 (13/589,786). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,86,499.PN.&OS=PN/83,86,499&RS=PN/83,86,499 Written by Amal Ahmed; edited by Jaya Anand.

*** Intel Assigned Patent ALEXANDRIA, Va., Feb. 27 -- Intel, Santa Clara, Calif., has been assigned a patent (8,386,701) developed by Raymond Scott Tetrick, Portland, Ore., Dale Juenemann, North Plains, Ore., and Robert Brennan, Portland, Ore., for an "apparatus and method for multi-level cache utilization." The abstract of the patent published by the U.S. Patent and Trademark Office states: "In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed." The patent application was filed on April 19, 2012 (13/450,882). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,386,701&OS=8,386,701&RS=8,386,701 Written by Arpi Sharma; edited by Anand Kumar.

*** InfoNovus Technologies Assigned Patent ALEXANDRIA, Va., Feb. 27 -- InfoNovus Technologies, Portland, Ore., has been assigned a patent (8,386,999) developed by Richard A. Skriletz, Portland, Ore., for a "method and system for analyzing a software design." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and system of analyzing a software design includes receiving one or more specifications containing one or more design elements. One or more design elements not included in the one or more specifications are identified. One or more design elements not included in the one or more specifications are generated. The one or more generated design elements are added to the one or more specifications." The patent application was filed on Aug. 11, 2008 (12/189,290). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,386,999&OS=8,386,999&RS=8,386,999 Written by Satyaban Rath; edited by Hemanta Panigrahi.

*** Cadence Design Systems Assigned Patent for Method, System, and Computer Program Product for Improved Electrical Analysis ALEXANDRIA, Va., Feb. 27 -- Cadence Design Systems, San Jose, Calif., has been assigned a patent (8,386,975) developed by four co-inventors for a "method, system, and computer program product for improved electrical analysis." The co-inventors are David White, San Jose, Calif., Matthew Liberty, Lake Oswego, Ore., Eric Nequist, Monte Sereno, Calif., and Michael McSherry, Portland, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "An improved method, system, user interface, and computer program product is described for using a memory and learning component to improve capacitance and resistance estimates based on the types of layouts and devices being evaluated. According to some approaches, a learning component is implemented that uses recommended test sets from the evaluation component to automatically test the extraction estimates against the field solver. Variability models from manufacturing or electrical analysis may also be used to select a series of objects (unique conductor geometries) that make up a conduction path or net or specific conductor geometries for evaluation and additional learning improvement." The patent application was filed on Dec. 26, 2008 (12/344,327). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,386,975.PN.&OS=PN/8,386,975&RS=PN/8,386,975 Written by Kusum Sangma; edited by Anand Kumar.

*** Cadence Design Systems Assigned Patent for Method and Systems for Implementing I/O Rings and Die Area Estimations ALEXANDRIA, Va., Feb. 27 -- Cadence Design Systems, San Jose, Calif., has been assigned a patent (8,386,981) developed by Miles P. McGowan, San Jose, Calif., and Thaddeus Clay McCracken, Portland, Ore., for a "method and systems for implementing I/O rings and die area estimations." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Disclosed are improved methods, systems, and computer program products for generating an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement." The patent application was filed on Dec. 23, 2010 (12/978,279). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,386,981.PN.&OS=PN/8,386,981&RS=PN/8,386,981 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Transmit Scaling Using Multiple Queues ALEXANDRIA, Va., Feb. 27 -- Intel, Santa Clara, Calif., has been assigned a patent (8,386,626) developed by Anil Vasudevan, Portland, Ore., Sujoy Sen, Portland, Ore., and Partha Sarangam, Portland, Ore., for a "transmit scaling using multiple queues." The abstract of the patent published by the U.S. Patent and Trademark Office states: "According to some embodiments, it may be determined, at a first processing element of a device with a plurality of processing elements, that first data is to be transmitted in association with a first network connection. A first entry associated with the first data may then be stored into a first of a plurality of transmit queues. It may subsequently be determined, at a second processing element of the device, that second data is to be transmitted in association with the first network connection. A second entry associated with the second data may then be stored into a second of the plurality of transmit queues." The patent application was filed on June 24, 2011 (13/168,403). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,386,626&OS=8,386,626&RS=8,386,626 Written by Arpi Sharma; edited by Anand Kumar.

*** International Business Machines Assigned Patent ALEXANDRIA, Va., Feb. 27 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,386,997) developed by Maged E. Elaasar, Kanata, Canada, and Jeffrey M. Fischer, Portland, Ore., for a "UML profile transformation authoring method and system." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and apparatus for authoring model-to-model transformations of programming models involving profiles is disclosed. Using a declarative mapping between a given profile of a subject programming model and a target profile of a target programming model, transformation of the given profile is specified and results in a declarative specification. Similarly the declarative mapping may be to a profile of a target programming model (without a corresponding source side profile) or from a profile of a source programming model (without a corresponding target side profile). Based on the declarative specification, a transformation code implementation (e.g. a transformation API) is generated. The given profile is specified as an input domain or as an output domain along with a meta model of the subject programming model. The generated transformation code implementation effectively handles complexities of dealing with the given profile at run time." The patent application was filed on Dec. 5, 2007 (11/951,075). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,386,997.PN.&OS=PN/8,386,997&RS=PN/8,386,997 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Method to Improve a Solid State Disk Performance by Using a Programmable Bus Arbiter ALEXANDRIA, Va., Feb. 27 -- Intel, Santa Clara, Calif., has been assigned a patent (8,386,650) developed by Richard P. Mangold, Forest Grove, Ore., for a "method to improve a solid state disk performance by using a programmable bus arbiter." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method to improve a solid state disk performance by using a programmable bus arbiter is generally presented. In this regard, in one embodiment, a method is introduced comprising delaying a request from a solid state drive for access to an interface for a time to allow a host to access the interface to transmit a command to the solid state drive. Other embodiments are described and claimed." The patent application was filed on Dec. 16, 2009 (12/639,700). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,386,650&OS=8,386,650&RS=8,386,650 Written by Arpi Sharma; edited by Anand Kumar.

*** Intel Assigned Patent for System and Method for Facilitating Wireless Communication During a Pre-boot Phase of a Computing Device ALEXANDRIA, Va., Feb. 27 -- Intel, Santa Clara, Calif., has been assigned a patent (8,386,618) developed by six co-inventors for a "system and method for facilitating wireless communication during a pre-boot phase of a computing device." The co-inventors are Abdul M. Bailey, Tigard, Ore., Di Tang, Shanghai, China, Rahul Khanna, Portland, Ore., Vincent J. Zimmer, Federal Way, Wash., Kevin Y. Li, Shanghai, China, and James W. Edwards, Portland, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system, device, and method for facilitating wireless communications during a pre-boot phase of a computing device includes establishing a communications interface between a unified extensible firmware interface executed on the computing device and a wireless transceiver of the computing device during a pre-boot phase of the computing device. An OOB processor of the computing device processes data communications between the unified extensible firmware interface and the wireless communication circuit during the pre-boot phase by reformatting the data communications between wired and wireless communication standards." The patent application was filed on Sept. 24, 2010 (12/889,583). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,386,618&OS=8,386,618&RS=8,386,618 Written by Arpi Sharma; edited by Anand Kumar.

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