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Rambus Unveils Developments in Memory Signaling TechnologyFeb 03, 2011 (Close-Up Media via COMTEX) -- Rambus, one of the world's largest technology licensing companies, announced it has advanced differential signaling for SoC-to-memory interfaces to 20 gigabits per second (Gbps) and developments which can extend single-ended memory signaling to 12.8Gbps. Rambus has also developed solutions which enable a transition for memory architectures from single-ended to differential signaling as data rates rise to meet the performance requirements of future-generation graphics and gaming systems. Rambus will demonstrate its developments in memory signaling technology this week at DesignCon 2011. The latest technology advancements of Rambus' Terabyte Bandwidth Initiative enable power efficiency and compatibility to single-ended memory architectures, including GDDR5 and DDR3. With the addition of FlexMode interface technology, a multi-modal, SoC memory interface PHY, supporting both differential and single-ended signaling, can be implemented in a single SoC package design with no additional pins. Rambus has achieved a power efficiency of 6 milliwatts (mW) per Gbps when operating at 20Gbps in a 40nm-process silicon test vehicle. These developments address critical system challenges to extending signaling rates by addressing power efficiency and compatibility needs. "We have paved multiple paths for the industry by providing solutions that extend single-ended signaling beyond today's limits and developing the means for an easy transition to differential signaling," said Sharon Holt, senior VP and general manager of the Semiconductor Business Group at Rambus. "By advancing data rates in an extremely power-efficient way, and enabling compatibility to current memories, we have removed the technical and business barriers for customers to achieve new capabilities in their products." Graphics cards and game consoles are the marquee performance products for consumers. The demand for photorealistic game play, 3D images, and a richer end-user experience is constantly pushing system and memory requirements higher. The graphics processors support as much as 128 gigabytes per second (GB/s) of memory bandwidth, and future generations will push memory bandwidth to upwards of one terabyte per second (TB/s). Through the Terabyte Bandwidth Initiative, Rambus has developed offerings using its signaling and memory architecture expertise. These Rambus patented developments include Fully Differential Memory Architecture (FDMA), FlexLink C/A and 32X data rate. The latest addition to these developments, FlexMode interface technology, enables support of both differential and single-ended memory interfaces in a single SoC package design. FlexMode technology achieves this with no additional pins through programmable assignment of signaling I/Os to either data or command/address. ((Comments on this story may be sent to [email protected])) |