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U.S. Patents Awarded to Inventors in Idaho (July 11)(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., July 11 -- The following federal patents were awarded to inventors in Idaho. *** Micron Technology Assigned Patent for for Encoding Transmitted Data Bits ALEXANDRIA, Va., July 11 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,766,828) developed by Timothy Hollis, Meridian, Idaho, for apparatus, systems and methods "to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms." The patent application was filed on Nov. 9, 2011 (13/292,276). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8766828.PN.&OS=PN/8766828&RS=PN/8766828 Written by Vessie Ann Abalos. *** SonoSite Assigned Patent ALEXANDRIA, Va., July 11 -- SonoSite, Bothell, Washington, has been assigned a patent (8,771,191) developed by Helmuth Fritz, Yucaipa, California, and Terry Fritz, Boise, Idaho, for an "ultrasonic blood vessel measurement apparatus and method." The patent application was filed on Oct. 28, 2004 (10/976,147). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,771,191.PN.&OS=PN/8,771,191&RS=PN/8,771,191 Written by Kusum Sangma; edited by Jaya Anand. *** Micron Technology Assigned Patent for Erasing Memory Cells Block ALEXANDRIA, Va., July 11 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,767,467) developed by nine co-inventors for a memory devices and methods "for erasing a block of memory cells." The co-inventors are Tejas Krishnamohan, Mountain View, California, Krishna K. Parat, Palo Alto, California, Jeremy Binfet, Boise, Idaho, Arnaud A. Furnemont, Boise, Idaho, Tyson M. Stichka, Boise, Idaho, Giuseppina Puzzilli, Boise, Idaho, Akira Goda, Boise, Idaho, Brian J. Soderling, Eagle, Idaho, and Koichi Kawal, Kanagawa, Japan. The patent application was filed on Aug. 19, 2013 (13/970,055). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8767467.PN.&OS=PN/8767467&RS=PN/8767467 Written by Vessie Ann Abalos. *** Micron Technology Assigned Patent for Stacked Microelectronic Dies ALEXANDRIA, Va., July 11 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,766,458) developed by David S. Pratt, Meridian, Idaho, for "stacked microelectronic dies employing die-to-die interconnects and associated systems and methods." The patent application was filed on Nov. 20, 2012 (13/682,019). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8766458.PN.&OS=PN/8766458&RS=PN/8766458 Written by Vessie Ann Abalos. *** Micron Technology Assigned Patent for Memory Devices ALEXANDRIA, Va., July 11 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,766,320) developed by three co-inventors for "memory devices with a connecting region having a band gap lower than a band gap of a body region." The co-inventors are Haitao Liu, Boise, Idaho, Jian Li, Boise, Idaho, and Chandra Mouli, Boise, Idaho. The patent application was filed on April 29, 2013 (13/872,762). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8766320.PN.&OS=PN/8766320&RS=PN/8766320 Written by Vessie Ann Abalos. *** Micron Technology Assigned Patent for Scanning Photolithography ALEXANDRIA, Va., July 11 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,767,179) developed by Wes McKinsey, Nampa, Idaho, for imaging methods "for scanning photolithography and a scanning photolithography device used in printing an image of a reticle onto a photosensitive substrate." The patent application was filed on Dec. 15, 2009 (12/638,094). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8767179.PN.&OS=PN/8767179&RS=PN/8767179 Written by Vessie Ann Abalos. *** Micron Technology Assigned Patent for Capacitors ALEXANDRIA, Va., July 11 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,766,347) developed by three co-inventors for "capacitors may include container-shaped storage node structures." The co-inventors are Duane M. Goodner, Boise, Idaho, Sanjeev Sapra, Boise, Idaho, and Darwin Franseda Fan, Boise, Idaho. The patent application was filed on Sept. 7, 2012 (13/607,230). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8766347.PN.&OS=PN/8766347&RS=PN/8766347 Written by Vessie Ann Abalos. *** Micron Technology Assigned Patent for Spin Torque Transfer Memory Cell ALEXANDRIA, Va., July 11 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,767,455) developed by two co-inventors for a "spin torque transfer memory cell structures and methods." The co-inventors are Stephen J. Kramer, Boise, Idaho, and Gurtej S. Sandhu, Boise, Idaho. The patent application was filed on Jan. 22, 2013 (13/746,402). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8767455.PN.&OS=PN/8767455&RS=PN/8767455 Written by Vessie Ann Abalos. *** Micron Technology Assigned Patent for Drain Select Gate Voltage Management ALEXANDRIA, Va., July 11 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,767,487) developed by three co-inventors for a "drain select gate voltage management." The co-inventors are Pranav Kalavade, San Jose, California, Akira Goda, Boise, Idaho, and Doyle Rivers, Meridian, Idaho. The patent application was filed on March 2, 2010 (12/715,530). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8767487.PN.&OS=PN/8767487&RS=PN/8767487 Written by Vessie Ann Abalos. *** Ovonyx Assigned Patent ALEXANDRIA, Va., July 11 -- Ovonyx, Sterling Heights, Michigan, has been assigned a patent (8,767,440) developed by Ward Parkinson, Boise, Idaho, and Thomas Trent, Nashua, New Hampshire, for "sector array addressing for ECC management." The patent application was filed on May 13, 2013 (13/892,499). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,767,440.PN.&OS=PN/8,767,440&RS=PN/8,767,440 Written by Balkishan Dalai; edited by Jaya Anand. *** Micron Technology Assigned Patent for Forming Phase Change Memory Circuitry ALEXANDRIA, Va., July 11 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,765,519) developed by three co-inventors for methods "of forming phase change materials and methods "for forming phase change memory circuitry." The co-inventors are Eugene P. Marsh, Boise, Idaho, Timothy A. Quick, Boise, Idaho, and Stefan Uhlenbrock, Boise, Idaho. The patent application was filed on Nov. 18, 2013 (14/083,084). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8765519.PN.&OS=PN/8765519&RS=PN/8765519 Written by Vessie Ann Abalos. *** Micron Technology Assigned Patent for Multi-port Memory ALEXANDRIA, Va., July 11 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,769,213) developed by two co-inventors for a "multi-port memory having an additional control bus for passing commands between ports." The co-inventors are Dan Skinner, Boise, Idaho, and J. Thomas Pawlowski, Boise, Idaho. The patent application was filed on Aug. 24, 2009 (12/546,258). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8769213.PN.&OS=PN/8769213&RS=PN/8769213 Written by Vessie Ann Abalos. *** Micron Technology Assigned Patent for Microfeature Workpiece Processing System ALEXANDRIA, Va., July 11 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,765,000) developed by two co-inventors for apparatus and methods "for microfeature workpiece processing system for semiconductor wafer analysis." The co-inventors are David A. Palsulich, Boise, Idaho, and Ronald F. Baldner, Boise, Idaho. The patent application was filed on July 9, 2010 (12/833,727). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8765000.PN.&OS=PN/8765000&RS=PN/8765000 Written by Vessie Ann Abalos. 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