[June 22, 2018] |
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Design Automation Conference 2018 Exhibitor Profiles
The 55th Design Automation Conference takes place 24 - 28
June, 2018 at the Moscone West Center in San Francisco. Please note
the following important information.
#55DAC Exhibitor News and Press Kits: http://www.tradeshownews.com/events/design-automation-conference-2018/
Information for Media: https://dac.com/media-center/exhibitor-news
Business Wire is the official news wire for DAC 2018. Listed below are
exhibitor profiles.
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Company:
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Agnisys Inc.
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Booth:
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1345
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Web:
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www.agnisys.com
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Agnisys Inc. is a leading supplier of Electronic Design Automation
(EDA) software for solving complex design and verification
problems for system development. Its products provide a common
specification-driven development flow to describe registers and
sequences for system-on-chip (SoC) and intellectual property (IP)
enabling faster design, verification, firmware, and validation.
Based on patented technology and intuitive user interfaces, its
products increase productivity and efficiency while eliminating
system design and verification errors.
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Founded in 2007, Agnisys is based in Boston, Massachusetts, with R&D
centers in the United States and India.
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Company:
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Austemper Design Systems
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Booth:
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2456
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Web:
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www.austemperdesign.com
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Austemper's comprehensive functional safety solution for
mission-critical systems in automotive, industrial, medical and
enterprise applications enables electronic hardware, integrated
circuit (IC) or intellectual property (IP) designers to meet the
challenges of functional safety. Its tools analyze designs for
various hardware metrics, indicate reasons for the metrics, identify
opportunities for enhancing the safety resilience of the design and
demonstrate results via fault injection and simulation. As an
integrated tool suite for functional safety, it addresses the entire
design cycle from concept to certification. DAC demonstrations will
highlight new capabilities to KaleidoScope to support analog design
for full concurrent mixed-signal fault propagation.
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Company:
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Baum Inc.
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Booth:
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2454
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Web:
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www.baum-ds.com
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Baum's PowerBaum, high-speed and accurate power modeling and
analysis solutions, enables engineering groups to fully optimize
the energy efficiency of their hardware designs. PowerBaum, Baum's
flagship product, addresses the three fundamental requirements of
power analysis -- automatic power model generation, high-speed
analysis and assurance of implementation accuracy across the
entire development phase. PowerBaum generates power models by
automatically learning and abstracting gate-level power behavior
to achieve a high level of accuracy while running orders of
magnitude faster than existing solutions in the market. The latest
product version, to be showcased at DAC, includes links to
hardware emulation to analyze and fix power "bugs" in realistic
software scenarios.
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Company:
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Blue Pearl Software, Inc.
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Booth:
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1457
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Web:
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www.bluepearlsoftware.com
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The Blue Pearl Visual Verification™ Suite provides advanced static
and formal linting, enhanced Clock Domain Crossing (CDC) analysis,
debug, and automated SDC generation to accelerate RTL verification.
The suite's Management Dashboard provides progress reports and
signoff statistics for audits and design reviews.
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This year, all new for DAC, Blue Pearl is showcasing its new HDL
Creator™ smart-editor. HDL Creator provides real-time syntax and
style code checking inside an intuitive, easy-to-use full featured
editor. Unlike standard editors, HDL Creator provides advanced
real-time file analysis, including over 2000 real-time checks to
find and fix issues as you code complex FPGAs, ASICs, IP and
testbenches.
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Company:
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Breker Verification Systems
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Booth:
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1419
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Web:
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www.brekersystems.com
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Breker's new Trek5 tool suite includes TrekSoC, TrekUVM, TrekSoC-Si
and "Apps," fully compliant with Accellera's Portable Stimulus
Specification (PSS) release 1.0. Trek5 leverages innovative
testbench and test synthesis technology to accelerate and simplify
complex test case generation for universal verification methodology
(UVM) and system-on-chip (SoC) verification flows. Scenario modeling
methods support PSS version 1.0 Domain Specific Language (DSL), C++
format and an extended native C++ mode. Model configuration
capabilities with scenario path constraints provide high-level
configurations of graph-based models, a hardware/software interface
(HSI) layer and enhanced procedural modeling options. Trek5 offers
Cache Coherency, Power Domain and ARMv8 Verification "TrekApps," and
integration with third-party simulators, emulators and debug
environments.
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Company:
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Cadence Design Systems (News - Alert), Inc.
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Booth:
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1308
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Ticker Symbol & Exchange:
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NASDAQ: CDNS
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Web:
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www.cadence.com
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Cadence enables electronic systems and semiconductor companies to
create the innovative end products that are transforming the way
people live, work and play. Cadence software, hardware and
semiconductor IP are used by customers to deliver products to market
faster. The company's System Design Enablement strategy helps
customers develop differentiated products-from chips to boards to
systems-in mobile, consumer, cloud datacenter, automotive,
aerospace, IoT, industrial and other market segments. Cadence is
listed as one of Fortune Magazine's 100 Best Companies to Work For.
Learn more at cadence.com.
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Company:
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Design Infrastructure Alley's Design-in-the-Cloud Pavilion
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Booth:
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1258
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Web:
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www.esd-alliance.org
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DAC's new Design-on-Cloud Pavilion, sponsored by Google (News - Alert) and
Microsoft, will feature presentations from Design Infrastructure
Alley exhibitors and invited companies during the three days of
exhibits. The pavilion will include a host of talks from senior IT
professionals and thought leaders about compute, licensing, storage,
security and cloud challenges. Executives from companies providing
goods and services that support the Design Infrastructure Alley will
offer presentations on hardware, software and services. A series of
discussions led by CAD and automation support professionals will
offer a look at developing and managing automation and tooling to
support design automation tools and flows.
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Company:
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Electronic System Design (ESD) Alliance
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Booth:
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1234
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Web:
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www.esd-alliance.org
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The ESD Alliance serves as the central voice to communicate and
promote the semiconductor design ecosystem's value as a vital
component of the global electronics industry. As an international
association of companies providing goods and services throughout the
semiconductor design ecosystem, it addresses technical, marketing,
economic and legislative issues affecting the industry. Its latest
newsletter will be available at its booth, offering information
about its expanding role within the semiconductor industry along
with updates on its charter, programs, initiatives and ongoing
events. Member companies and companies interested in joining are
invited to stop by to pick up this year's giveaways.
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Company:
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Mentor, a Siemens (News - Alert) Business
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Booth:
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2621
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Web:
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www.mentor.com
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Mentor, a Siemens business, is a world leader in electronic hardware
and software design solutions, providing products, consulting
services, and award-winning support for the world's most successful
electronic, semiconductor, and systems companies. Visit us at DAC
and learn about emulation in the cloud, developments in automotive
functional safety and more.
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Company:
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OpenText
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Booth:
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1424
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Ticker Symbol & Exchange:
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NASDAQ: OTEX, TSX: OTEX
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Web:
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https://www.opentext.com/connectivity
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OpenText™ Connectivity products, formerly Hummingbird, provide fast,
reliable access to a variety of enterprise applications, including
host systems such as UNIX® and Linux®, Microsoft (News - Alert)® Windows®,
mainframes, network file systems and more.
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At DAC San Francisco 2018, OpenText Connectivity is showcasing
Exceed TurboX, a high performance remote access solution for
graphically demanding EDA software solutions.
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OpenText Exceed TurboX makes UNIX®, Linux and Windows® applications
accessible through the web, so your business can empower its global
workforce with a high-performance remote access solution. Exceed
TurboX enables organizations to save costs by consolidating
applications into the data center with minimal disruption to the
business.
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Company:
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Plunify
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Booth:
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2124
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Web:
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www.plunify.com
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Software solutions from Plunify enable designers to meet FPGA design
performance targets, shorten product time to market and reduce
development costs with no disruption to existing workflows. It
solves complex chip design timing and performance problems through
machine learning techniques for communications, data center
applications and applications such as high-end test and measurement
equipment, advanced driver assistance systems (ADAS) and
high-frequency trading (HFT). Plunify's portfolio includes EDAxtend
chip design and InTime timing closure tools and InTime Service. The
Plunify Cloud Platform offers abundant, affordable licensing and
compute resources for FPGA designers to apply machine learning
techniques with InTime to optimize their designs.
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Company:
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RISC-V Foundation
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Booth:
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2638
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Web:
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https://riscv.org/
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RISC-V (pronounced "risk-five") is a free and open ISA enabling a
new era of processor innovation through open standard collaboration.
Founded in 2015, the RISC-V Foundation comprises more than 100
member organizations building the first open, collaborative
community of software and hardware innovators powering innovation at
the edge forward. Born in academia and research, RISC-V ISA delivers
a new level of free, extensible software and hardware freedom on
architecture, paving the way for the next 50 years of computing
design and innovation.
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The RISC-V Foundation, a non-profit corporation controlled by its
members, directs the future development and drives the adoption of
the RISC-V ISA. Members of the RISC-V Foundation have access to and
participate in the development of the RISC-V ISA specifications and
related HW / SW ecosystem.
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Company:
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Verific Design Automation
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Booth:
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2311
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Web:
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www.verific.com
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Verific's will showcase "Verific with INVIO," the full integration
of INVIO with its flagship SystemVerilog, VHDL and UPF parser
platform. INVIO, a collection of high-level Python APIs, enables
Verific users to simplify and streamline their design environment,
accelerating tool development. SystemVerilog- and VHDL-language
agnostic INVIO offers a high level of abstraction that CAD support
departments need for their SystemVerilog and VHDL flows. Verific's
parser platforms are used as the front-ends of choice in many
electronic design automation (EDA) and field programmable gate array
(FPGA) tools. Applications range from analysis, simulation, formal
verification and synthesis to emulation and virtual prototyping,
in-circuit debug and design for test.
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