Cadence Solutions Help SandLinks to Develop Low-Power Silicon

Cadence Design Systems (News - Alert) today announced that SandLinks has designed functional silicon of low-power Radio Frequency Identification (RFID) tag device that was implemented using common power format (CPF)-enabled Cadence Low-Power Solution.

 

Cadence Low-Power Solution, which SandLinks used, consists of Encounter RTL Compiler global synthesis, Encounter Conformal Low Power and SoC Encounter RTL-to-GDSII system. For the design and implementation of the radio part of its ultra wideband (UWB) transceiver, SandLinks used Cadence Virtuoso custom design platform. Using these solutions, SandLinks was able to achieve key requirements for this chip, including ultra-low power consumption and longer battery life for the active RFID tag (News - Alert).

 

Cadence Encounter RTL compiler global synthesis predicts and optimizes power consumption. SandLinks used CPF during silicon verification process, to verify, among other things, the on-off functionality of the chip. The tapeout was on time, and silicon results demonstrated the functionality of SandLinks' UWB transceiver, enabling the company to proceed with the testing and manufacturing of the RFID system.

 

“Using CPF, our engineers described the power intent as part of the RTL delivery to the back-end design house, shortening the loops, providing consistent guidance and avoiding misunderstanding between the front-end and back-end engineers,” said Gideon Kaplan, co-founder and vice president of research and development, SandLinks. “The proof of the flow is our successful silicon. We estimate that we were able to save about 10 weeks of precious design time by using Cadence's CPF-based low-power design flow.”

 

Chi-Ping Hsu, Cadence corporate vice president, IC Digital and Power Forward, said, “This design provides yet another perfect example of the value of the Cadence Low-Power Solution -- first-time right silicon on time. The Cadence Low-Power Solution has been production proven and used successfully in production at more than 50 companies.”

 

Cadence Low-Power Solution combines a variety of Cadence technologies that leverage Si2 Common Power Format, which specifies power-saving techniques early in the design process -- enabling design teams to share and reuse low-power intelligence.

 

“The low-power design methodology, with the Si2 Common Power Format as a basis, enables these companies to quickly deliver highly competitive ultra-low-power products to their markets,” added Hsu.

 

Cadence provides software, hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. To help design teams adopt advanced power-management techniques, Cadence offers complete solution for the design, verification, and implementation of low-power chips.