Digital Core Design, an intellectual property and System-on-a-Chip design house, recently added the DP8051, a high-performance, speed-optimized soft core of a single-chip 8-bit embedded controller, to its portfolio.

The simple and highly efficient DP8051 runs the Dhrystone 2.1 benchmark program 11.46 to 15.55 times faster, executing up to 300 million instructions per second. Officials said that it also operates with both fast and slow memories.

The additional features and peripherals of the DP8051 allow engineers to adapt the core to the specific application and/or hardware requirements. The core has been designed with a special concern about power to performance ratio, which is extended by an advanced power management PMU unit.

In a statement, Tomasz Krzyzak, VP, Member Board of Directors at Digital Core Design, said, “Also there's a bunch of serviceable peripherals available e.g. 2-15 interrupt sources, 4 interrupt levels, 2 data pointers, USB device, Ethernet controller, up to 4 timer/counters, 2 UARTs, 4 I/O ports and more. Depending on the configuration, the designer can likewise choose from e.g. compare/capture, watchdog, master/slave I2C Bus controller, Quad SPI, fixed point copro-cessor or a floating point coprocessor.”

With a built-in support for the DoCDTM Hardware De-bugger, the DP805 provides debugging capability of a whole System on Chip.

Officials said that the DoCDTM offers non-intrusive debugging of a running application and can also efficiently save designer's time owing to a hardware trace known as Instructions Smart Trace buffer.

In related TMC (News - Alert) news, ChipStart, LLC, a provider of semiconductor intellectual property and Digital Core Design, entered into a partnership to bring the power of innovation to the market through a joint relationship.