IntellaSys, the technology development arm of the TPL Group, has introduced SEAforth 40C18 multicore processor technology for next-generation embedded wireless, portable and distributed data processing applications. The SEAforth 40C18 is an array of 40 fully functional CPUs, operating asynchronously on a monolithic die.
Today’s high-data throughput requirements, in a wide range of consumer electronics, networking, automotive and defense applications, demand the speed, power and size advantages of the SEAforth 40C18 design. The chip is currently in beta testing at some OEMs. When designing devices for embedded automotive applications, the designers have to keep the power consumption in mind.
Companies such as BMW Technology Office Palo Alto (News
) discovered that SEAforth 40C18 delivers advanced filtering capabilities at a fraction of the power consumed by other products available in the market today. They discovered this while running tests on edge filtering for automotive imaging applications.
SEAforth will be offered with VentureForth, an advanced multicore integrated development environment (IDE). This includes interactive programming, testing and debugging facilities. While drawing 7mW of power or less per CPU, the SEAforth 40C18 is capable of executing 80 percent of its VentureForth instructions in 1.38 nanoseconds.
Its technology sets the performance paradigm of the future for high-speed parallel execution capabilities based on the IntellaSys Scalable Embedded Array (SEA) platform. This includes better performance per watt, low power consumption and low-cost benefits.
The SEAforth chip consumes 28 times less power and runs 240 times faster than competing architectures as it features the smallest core size design (0.13 mm2). By creating a RAM and ROM on each core, the SEAforth 40C18 breaks the memory bottleneck. Instead of being throttled down to a slower external system clock frequency, this facilitates individual cores to run at the full native speed of the silicon. The SEAforth 40C18 is slated for December 2008 availability.
“The beauty of this single-chip 40 CPU processing solution is that it is completely programmable – meaning if a spec changes, it is a code issue, not a silicon turn,” said Charles Moore, chief technology officer of IntellaSys. “With 40 cores operating independently on the chip, designers can dedicate groups of them to handle specific tasks. For example, some could be assigned compute-intensive Fast Fourier Transforms (FFT) while others handle wireless connectivity, standard I/O interfaces or drive external memory.”
Raju Shanbhag is a contributing editor for TMCnet. To read more of Raju's articles, please visit his columnist page.
Edited by Eve Sullivan